Simulation analysis of the Intel 22nm FinFET

On 23^th April Chipworks posted a blog revealing the inner workings of the Intel 22 nm technology and the architecture of the corresponding FinFETs or, as Intel calls them, tri-gate transistors.

Figs 5, 6 and 7 in the Chipworks posting compare the “unexpected” slope of the fabricated transistors with the original tri-gate schematic shown by Intel last year. There is a lot of speculation about the possible advantages and disadvantages of the trapezoidal (or almost triangular) shaped ‘bulk’ FinFET.

Driven by natural curiosity we decided to shine some light on these questions by doing 3D simulations with our ‘atomisic’ simulator GARAND, although at this initial stage the ‘atomicity’ doesn’t play any role in our simulations. Fig 1 compares the TEM image of one of the FinFETs from Fig. 7 of the Chipworks posting with our simulation domain. Since we do not have information about the doping distribution in the Intel FinFETs we have assumed a lightly doped channel, which is beneficial from the point of view of statistical variability.

Fig. 1 Comparison of the TEM image of one of the FinFETs from Fig. 6 of the Chipworks blog with the GARAND simulation domain.

The electron concentration and the potential distribution along the fin are illustrated in Fig.2. We have assumed that there is a high doping concentration stopper below the fin in the STI region. Clearly FinFETs are more complicated devices in terms of understanding and visualisation compared to the ‘old’ bulk MOSFETs.

Fig. 2 Electron concentration and the potential distribution along the fin.

The current density distribution across the fin in the middle of the channel at different gate bias conditions is illustrated in Fig. 3 and is rather complex. At low gate voltage the maximum current density is in the middle of the channel where the gate has least control over the turning-off of the device. The depletion region caused by the highly-doped stopper below the channel prevents current flow at the very bottom of the channel – one drawback of the bulk FinFET architecture. At high gate voltage the current moves towards the interface, crowding at the top of the fin due to the focusing gate fringing field there, with quantum mechanical confinement concentrating the charge in a small circular region. Fig. 4 animates the changing gate bias, focussing on the fin channel.

Fig. 3 Current density distribution across the Fin at different gate bias conditions.

Fig. 4. Close-up view of the fin with an animation of the current density with increasing gate bias.

Undoubtedly the result that we found most interesting is the comparison in Fig. 5 between the gate length dependence of the threshold voltage for the trapezoidal Intel transistor and an equivalent rectangular-fin transistor (same fin height and with fin width equal to the average width of the trapezoidal fin). Clearly the rectangular fin has better short channel effects. Still, the million dollar question is if the almost-triangular shape is ‘on purpose’ design, or is this what bulk FinFET technology can achieve in terms of the fin etching?

Fig. 5 Threshold voltage dependence on gate length comparing the Intel-type structure with an ideal rectangular FinFET.

We would be delighted to hear your opinions on this interesting device, particularly with regard to the shape.