Bulk CMOS at 28nm, and particularly at 20 nm, are extremely power hungry, and the FinFET technology is somewhere in the ‘bright but distant future’. For many of the fabless companies planar fully depleted silicon-on-insulator (FD-SOI) is becoming a very attractive solution at the late stage of 28nm and the early stage of 20nm.

True to our mission, GSS has investigated the expected statistical variability in 32/28nm FD-SOI transistors in comparison to equivalent bulk MOSFETs. We have studied the differentiation between metal-gate-first and metal-gate-last flavours of the technology. The transistor design is based on the EC FP7 project PULLNANO [1], which focused on the development of 32nm CMOS technology in Europe, and is benchmarked in respect of experimental data published by LETI [2]. The simulations are carried out with our ‘atomistic’ 3D simulator GARAND.

The simulations include random dopants, line edge roughness and metal gate granularity as the main sources of statistical variability. The unmistakable advantage and value of the 3D ‘atomistic’ simulation is revealed in Fig. 1, which illustrates the impact of the different variability sources on the potential and the carrier concentration distributions in the simulated FD-SOI MOSFET.

Fig. 1: Impact of the different variability sources on the potential and the carrier concentration distributions in the simulated FD-SOI MOSFET

The important messages revealed by the simulations are as follows. The statistical variability introduced by the random discrete dopants in the FD-SOI MOSFETs is significantly lower compared to bulk MOSFETs with equivalent dimensions. This is illustrated in Fig. 2 where the current-voltage characteristic of 1000 FD-SOI transistors with 32 nm channel length are superimposed on top of the characteristics of bulk transistors with identical threshold voltage and very similar short-channel effects. Only the unavoidable impact of random dopants is considered in the simulations.

 a)VD=50 mV a) VD=1 V Fig. 2: Current-voltage characteristics of 1000 bulk and FD-SOI transistors with 32 nm channel length subject to random discrete dopants

The improvement is dramatic. The threshold voltage variation is reduced more than 6 times and the leakage is reduced 5 times for almost equivalent drive current. There is, however, an important peculiarity in the FD-SOI variability. The small threshold voltage variation does not automatically mean small on-current variation. The disproportionate on-current variation in the FD SOI transistors, particularly at low drain voltage, is associated with the random dopants in the access region between the gate and the contacts. Fluctuation in the number of random dopants results in access resistance variation and corresponding on-current variation.

Still, the reduction of statistical variability in the FD-SOI transistor looks “too good to be true”, and you would be right to say so. There are another two important sources of statistical variability: line edge roughness and the metal gate granularity. Their impact on the statistical variability of the FD-SOI transistor is illustrated in Fig. 3. The blue group of curves in this figure reflects only the impact of the random discrete dopants.

The red group represents the combined effect of random discrete dopants and line edge roughness. This is the variability expected in a metal-gate-last version of the FD-SOI technology where the metal gate will not suffer high temperature treatments and could be kept amorphous.

Finally the grey group represents the combined effect of random discrete dopants, line edge roughness and metal gate granularity. This is what you should expect from the metal-gate-first flavour of the FD-SOI technology.

 a) VD=50 mV a) VD=1 V Fig. 3: Current-voltage characteristics of 1000 bulk and FD-SOI transistors with 32 nm gate length, subject to the combined effect of different variability sources.

Simulations of course are good, but there is nothing better than silicon. So here is the moment of truth that we would like to prepare you for. The statistical variability is measured and compared usually using a single figure of merit, the AVT factor. The AVT factor tells you how the threshold voltage standard deviation depends on the transistor geometry for a particular CMOS technology:

$$\sigma V_{T}=\frac{A_{VT}}{\sqrt{2WL}}$$

where W and L are the gate width and gate length respectively. A well-designed bulk technology at 32/28 nm will have an AVT factor in the range of 2.5 to 3.0mV.μm. The experimentally measured metal-gate-first FD-SOI AVT factor reported by LETI [2] is very close to 1.0mV.μm, which is in excellent agreement with our simulations. To date, there are no FinFET results with a better AVT factor to have been published.

However our simulations reveal that if you can develop a metal-gate-last 28nm FD-SOI technology you will be able to achieve the astonishing AVT factor in the range of 0.5-0.6mV.μm.

What does all this mean for the power dissipation and, particularly, the supply voltage of SRAM. Starting with bulk at 28 nm you need approximately 0.9V to secure the reliable operation of large SRAM arrays. With metal-gate-first FD-SOI you will be able to reduce this voltage to below 0.7V. However the technologist who that could develop and deliver metal-gate-last FD-SOI at 28nm will be able to offer you supply voltage below 0.5V.

The AVT factor for the different flavours of the 28nm bulk and FD-SOI technologies are summarised in Table 1 together with the expected VCCmin of the corresponding minimal area SRAM cells.

Table 1: AVT factor and VCCmin for the different flavours of the 28nm bulk and FD-SOI technologies

 Bulk FD-SOI AVT [mV.μm] VCCmin [V] AVT [mV.μm] VCCmin [V] Gate first 2.9 1.0 1.2 <0.7 Gate last 2.5 0.9 0.6 <0.5