In our last two blog posts we discussed the triangular shape of the Intel bulk FinFETs and its implications for the transistor performance compared to ‘ideal’ rectangular-shaped transistors. The main observations included:
- a worsening of the short channel effects
- a reduction in the on-current by 12-15% compared to rectangular-gate bulk FinFETs
One question that many people are asking is ‘assuming that you can make ideal rectangular bulk and SOI FinFETs, which one will have better performance?’ Here we provide some answers, assuming bulk and SOI FinFET designs illustrated schematically in Fig. 1 with exactly the same geometry of the fin and with undoped channels. The nominal device dimensions are LG=20nm, Wfin=10nm and Hfin=25nm.
Fig. 1 (a) Bulk and (b) SOI FinFET design
The main difference between the two devices is the presence of a stopper beneath the channel in the bulk FinFET case, which prevents drain-induced barrier lowering (DIBL) and improves the short-channel effects of the bulk FinFET. The presence of the SOI substrate eliminates the need for such a stopper in the case of the SOI FinFET.
Figure 2 compares the current IODsat in the bulk and SOI FinFETs at the same gate overdrive voltage, which is the difference between the threshold voltage and the supply voltage. The overdrive current is a good indication about the speed of the corresponding circuits at matched threshold voltage and leakage current. The SOI FinFETs deliver, on average, 5% higher drive current depending on the actual design of the fin geometry.
Fig. 2 Detailed comparison of the IODsat boost for SOI compared to bulk
An alternative way to compare the performance is to look at the leakage current in the case of transistors with the same performance. This is an indication of how long the batteries will last in standby mode for two circuits with the same performance. According to Fig. 3 the SOI FinFETs deliver, on average, 2.5 times smaller leakage, which could more than double the battery life of your mobile phone.
Fig. 3 Comparison of leakage current between SOI and bulk FinFETs with matched ION performance.
Fig. 4 provides the physical explanation for these findings. The necessary presence of the stopper below the channel in the bulk fin leads to the carriers being pushed up towards the top of the fin (due to the built-in potential between the undoped channel and the highly-doped stopper), reducing the effective channel width and somewhat reducing the FinFET performance for the same physical fin height.
Fig. 4 Comparison of the current density in a cross-section across the middle of the bulk and SOI FinFETs
The detailed design of the 20nm channel length FinFETs simulated in this blog as well as the optimal design of 14nm and 10nm bulk and SOI FinFETs are described in a report available here.
July 27, 2012 | Share: